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< #include <rt_mmap.h>
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< 	//DECLARE_GLOBAL_DATA_PTR;
---
> 	DECLARE_GLOBAL_DATA_PTR;
> 
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< 	u32 reg, cpu_clock = 0;
< #if defined(RT2880_ASIC_BOARD) || defined(RT2883_ASIC_BOARD) || defined(RT3052_ASIC_BOARD)
---
> 	int i;
> 	u32 reg,cpu_clock;
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< #endif
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> 	 *		11: 300Mhz
> 	 *      10: 280Mhz
> 	 *      01: 250Mhz
> 	 *      00: 233Mhz
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< #ifdef RT2880_FPGA_BOARD
---
> #ifdef FPGA_BOARD_RT2880
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< #elif defined (RT2883_FPGA_BOARD) || defined (RT3052_FPGA_BOARD)
< 	cpu_clock = 40 * 1000 * 1000;
< 	mips_bus_feq = cpu_clock / 3;
< #elif defined(RT2883_ASIC_BOARD) 
< 	clk_sel = (reg>>20) & 0x03;
< 	switch(clk_sel) {
< 		case 0:
< 			cpu_clock = (380*1000*1000);
< 			break;
< 		case 1:
< 			cpu_clock = (400*1000*1000);
< 			break;
< 		case 2:
< 			cpu_clock = (420*1000*1000);
< 			break;
< 		case 3:
< 			cpu_clock = (430*1000*1000);
< 			break;
< 	}
< 	mips_bus_feq = cpu_clock / 2;
< #elif defined(RT3052_ASIC_BOARD)
< 	clk_sel = (reg>>18) & 0x01;
< 	switch(clk_sel) {
< 		case 0:
< 			cpu_clock = (320*1000*1000);
< 			break;
< 		case 1:
< 			cpu_clock = (384*1000*1000);
< 			break;
< 	}
< 	mips_bus_feq = cpu_clock / 3;
< #else /* RT2880 ASIC version */
---
> #else
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< #ifdef RT2880_MP
---
> #ifdef RT2880_FPGA_B_VER_BOARD
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< #else /* RT2880 SHUTTLE */
---
> #else
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<    	//RT2882_REG(RT2880_SYSCFG_REG) = reg;
---
>    	RT2882_REG(RT2880_SYSCFG_REG) = reg;
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< 	//reset uart lite and uart full
< #if defined(RT2880_ASIC_BOARD) || defined(RT2880_FPGA_BOARD)
< 	*(unsigned long *)(RALINK_SYSCTL_BASE + 0x0034) = cpu_to_le32(1<<12);
< #elif defined(RT2883_ASIC_BOARD) || defined(RT2883_FPGA_BOARD) || defined(RT3052_ASIC_BOARD) || defined(RT3052_FPGA_BOARD)
< 	*(unsigned long *)(RALINK_SYSCTL_BASE + 0x0034) = cpu_to_le32(1<<19|1<<12);
< #else
< #error "undefined Platform"
< #endif
< 	/* RST Control change from W1C to W1W0 to reset, update 20080812 */
< 	*(unsigned long *)(RALINK_SYSCTL_BASE + 0x0034) = 0;
< 	//clock_divisor = (CPU_CLOCK_RATE / SERIAL_CLOCK_DIVISOR / gd->baudrate);
---
> 
> 	//reset uart lite
> 	my_tmp = le32_to_cpu(*(unsigned long *)(0xa0300034));
> 	*(unsigned long *)(0xa0300034) = cpu_to_le32(my_tmp |0x00001000);
> //	clock_divisor = (CPU_CLOCK_RATE / SERIAL_CLOCK_DIVISOR / gd->baudrate);
